1. Field of the Invention
The present invention relates to memory cells and, in particular, to multiple access memory cells with multiple write- and read-access ports.
2. Description of the Related Art
Computer memory cells are in wide use today. They may be used, for example, in random-access memory (RAM), in registers, and other devices. Each memory cell stores a bit of data, i.e. a 0 (low, typically V.sub.SS or ground (0V)) or 1 (high, typically V.sub.DD). New data may be written into the cell, and stored data may be read from the cell. A row of memory cells is typically used to provide storage of larger, multi-bit units of data such as bytes or words. An array of memory cells can provide a number of rows or words to provide multiple word storage.
Referring now to FIG. 1, there is shown a circuit diagram illustrating a prior art memory cell 100. Memory cell 100 comprises a flip-flop or memory element comprising inverters 101, 102, which may be implemented with two transistors each (one nmos and one pmos transistor). The flip-flop has data node D and inverse-data node DN (data-not, the inverse of D). Data node D stores a 1 or 0 corresponding to the data stored in memory cell 100.
Cell 100 comprises at least one data access port such as the data access port illustrated in FIG. 1, which allows a single external device or component such as a processor to write or read a bit to the cell, at a given time. The term data access port (or access port) is used to refer to both write and read data access ports, that is, a data access port used to perform a read or write of data. A data access port used to write data may be referred to as a write-access port, and a data access port used to read data may be referred to as a read-access port.
The data access port illustrated in FIG. 1 comprises nmos access transistors 105, 106, plus four input lines for the three signals BIT, BIT, and WL (Word-Line), for purposes of writing a bit to or reading a bit from memory cell 100, from or to a single external device such as a processor. The memory cells of a given column of an array of memory cells typically share the same data access ports.
Cell 100 may be powered by a power supply voltage of, say, V.sub.DD =3V. Nmos transistors such as transistors 105, 106 have a typical threshold drop of approximately 0.6V. Due to the threshold voltage of access transistor 105, the input signal on a single input line BIT may not be strong enough to write a 1 quickly enough, or even at all. For example, if cell 100 previously stored a 0 so that data node D was 0V, and a 1 is to be written to the cell by input line BIT, then a 1 (3V) on line BIT causes node D to raise from 0V to only 2.4V, because of the voltage drop of 0.6V across transistor 105. Increasing node D to 2.4V may be too low to quickly raise the cell to a 1 state from a 0 state, because it may be slow to overcome the current 0 state of the cell.
Even worse, with even lower supply voltages such as 1.2V, node D would only be raised to 0.6V, which is insufficient to guarantee that node D is pulled high quickly enough or even at all. With smaller and smaller supply voltages, because of the voltage drop of the access transistor of the data access port, a single input line is unable, in the prior art, to override the previous 0 state to write a 1 state.
Thus, two input lines, BIT and BIT, are typically used to store the signal provided by the BIT line in a memory cell such as cell 100. To store a value in cell 100, signal WL goes high, and BIT provides the signal to be stored, while BIT provides the inverse of the BIT signal. In the case where D was is 0 from the previous memory state, and BIT carries a 1 (1.2V) to be stored in cell 100, BIT is 0V and so is node DN, because there is no voltage drop across transistor 106 when BIT is 0. A 0 or low signal at the input to inverter 102 causes inverter 102 to bring node D quickly up to 1. Thus, each write-access port requires two access transistors such as transistors 105, 106 plus four input lines carrying three input signals. For a write operation, the BIT signal is derived from the data signal provided by the processor writing into the cell. The BIT signal is provided by an inverter external to the memory cell array. The WL signal is provided by memory control logic which itself receives address information from the processor.
Similarly, the data access port may be used as a read-access port. In this case access transistors 105, 106 serve as read-access transistors. To read the state or bit of cell 100, an output line coupled to each of the BIT and BIT terminals has to be precharged. Then, the read-access transistors 105, 106 are turned on, allowing the cell to discharge one of the two precharged lines, depending on whether the cell is high or low. When a line is discharged, external circuitry can detect this and thus will be able to tell whether the memory cell 100 has a 0 or 1 stored therein.
Other memory cells in the same column (bit position) as cell 100 comprise a similar data access port and are coupled to the same BIT and BIT lines for the port. Thus, it is not possible for a single processor to access cell 100 and another cell in the same column but in a different row (word) using the same port, at the same time. For this reason, each processor is typically coupled to at least two ports per memory cell, so that it can access one cell using one of the two ports and access the other cell using the other port. The processor itself has at least two data ports by which it couples to the two different memory ports of each memory cell. This means that each processor is coupled by its two data port lines to each memory cell column, and each cell has 8 port lines or terminals for the processor.
Memory cells are often implemented in computer systems having multiple processors or other units, each of which may need to simultaneously read from and/or write into the array of memory cells. For example, each of four processors may need to write or read from four different words or rows of the memory cell array. Alternatively, one or more processors may wish to read simultaneously from the same cell while it is being written by another processor. There is thus a need for multiple access memory cells, that is, memory cells with sufficient read and write data access ports to allow multiple external units such as processors to be able to simultaneously read from and/or write to the memory cell array.
As explained previously, each memory cell may require 2 access ports (i.e., 4 access transistors and 8 terminals) for each processor. Thus, for multiple processors, each memory cell requires two access ports and 8 terminals per processor. For example, If 4 processors are to be able to access cell 100, this requires 4.times.2=8 ports (i.e. 4.times.4=16 access transistors and 4.times.8=32 signal terminals) per memory cell.
One problem with this conventional memory cell design is that many transistors and terminals must be added for each additional data access port and processor of the system. The large number of access port transistors and terminals increases chip (and PCB) area and power consumption. The necessity of precharging two read lines and of always discharging one of the two for each read also consumes a large amount of power. Further, during a write-through operation, where one processor writes cell 100 while another processor simultaneously reads the data being written to memory cell 100 via a second access port, the load on nodes D and DN imposed by the second access port can slow down the speed of writing the new data to the cell.